[Balloon-svn] r1161 - balloon/branches/menuconfig/kernel/2.6…

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Author: subversion@balloonboard.org
Date:  
To: balloon-svn
Subject: [Balloon-svn] r1161 - balloon/branches/menuconfig/kernel/2.6.25.2
Author: nick
Date: 2010-06-14 13:13:22 +0100 (Mon, 14 Jun 2010)
New Revision: 1161

Modified:
balloon/branches/menuconfig/kernel/2.6.25.2/balloon3-nand.patch
balloon/branches/menuconfig/kernel/2.6.25.2/balloon3.patch
Log:
update nand access glue for new FPGA addresses 

Modified: balloon/branches/menuconfig/kernel/2.6.25.2/balloon3-nand.patch
===================================================================
--- balloon/branches/menuconfig/kernel/2.6.25.2/balloon3-nand.patch    2010-06-14 10:26:04 UTC (rev 1160)
+++ balloon/branches/menuconfig/kernel/2.6.25.2/balloon3-nand.patch    2010-06-14 12:13:22 UTC (rev 1161)
@@ -1,7 +1,7 @@
 Index: drivers/mtd/nand/Makefile
 ===================================================================
---- drivers/mtd/nand/Makefile.orig    2010-06-12 06:12:32.000000000 +0100
-+++ drivers/mtd/nand/Makefile    2010-06-12 06:17:59.000000000 +0100
+--- drivers/mtd/nand/Makefile.orig    2008-05-07 00:21:32.000000000 +0100
++++ drivers/mtd/nand/Makefile    2010-06-13 19:42:12.000000000 +0100
 @@ -28,6 +28,7 @@
  obj-$(CONFIG_MTD_NAND_CM_X270)        += cmx270_nand.o
  obj-$(CONFIG_MTD_NAND_BASLER_EXCITE)    += excite_nandflash.o
@@ -12,8 +12,8 @@
  obj-$(CONFIG_MTD_NAND_ORION)        += orion_nand.o
 Index: drivers/mtd/nand/Kconfig
 ===================================================================
---- drivers/mtd/nand/Kconfig.orig    2010-06-12 06:12:32.000000000 +0100
-+++ drivers/mtd/nand/Kconfig    2010-06-12 06:17:59.000000000 +0100
+--- drivers/mtd/nand/Kconfig.orig    2008-05-07 00:21:32.000000000 +0100
++++ drivers/mtd/nand/Kconfig    2010-06-13 19:42:12.000000000 +0100
 @@ -290,6 +290,10 @@
        Enables support for NAND Flash interface on PA Semi PWRficient
        based boards
@@ -28,8 +28,8 @@
 Index: drivers/mtd/nand/balloon3.c
 ===================================================================
 --- /dev/null    1970-01-01 00:00:00.000000000 +0000
-+++ drivers/mtd/nand/balloon3.c    2010-06-12 06:34:53.000000000 +0100
-@@ -0,0 +1,286 @@
++++ drivers/mtd/nand/balloon3.c    2010-06-14 12:17:21.000000000 +0100
+@@ -0,0 +1,307 @@
 +/*
 + * linux/drivers/mtd/nand/balloon3.c
 + *
@@ -65,12 +65,15 @@
 +#define SPLIT_RANGE_SIZE    0x1000
 +//#define SPLIT_RANGE_SIZE    4
 +
-+#define balloon3_phys_ctl_base (BALLOON3_NANDIO_PHYS + BALLOON3_NANDIO_CTL_OFFSET)
++#define balloon3_phys_ctl_clr_base (BALLOON3_NANDIO_PHYS + BALLOON3_NANDIO_CTL_CLR_OFFSET)
++#define balloon3_phys_ctl_set_base (BALLOON3_NANDIO_PHYS + BALLOON3_NANDIO_CTL_SET_OFFSET)
 +#define balloon3_phys_io_base (BALLOON3_NANDIO_PHYS + BALLOON3_NANDIO_IO_OFFSET)
 +static void __iomem *balloon3_io_base = (void __iomem *)(BALLOON3_NANDIO_VIRT + BALLOON3_NANDIO_IO_OFFSET);
-+static void __iomem *balloon3_ctl_base = (void __iomem *)(BALLOON3_NANDIO_VIRT + BALLOON3_NANDIO_CTL_OFFSET);
++static void __iomem *balloon3_ctl_clr_base = (void __iomem *)(BALLOON3_NANDIO_VIRT + BALLOON3_NANDIO_CTL_CLR_OFFSET);
++static void __iomem *balloon3_ctl_set_base = (void __iomem *)(BALLOON3_NANDIO_VIRT + BALLOON3_NANDIO_CTL_SET_OFFSET);
 +#define FLASHIO         balloon3_io_base    /* Flash I/O */
-+#define FLASHCTL    balloon3_ctl_base    /* Flash Control */
++#define FLASHCTL_CLR    balloon3_ctl_clr_base    /* Flash Control Clear */
++#define FLASHCTL_SET    balloon3_ctl_set_base    /* Flash Control Set */
 +#else
 +#define balloon3_phys_nand_base (BALLOON3_NANDIO_PHYS)
 +static void __iomem *balloon3_nand_base = (void __iomem *)(BALLOON3_NANDIO_VIRT);
@@ -149,9 +152,11 @@
 +            clear_ctl |= FLALE;
 +
 +        if (clear_ctl)
-+            __raw_writel(clear_ctl, BALLOON3_NAND_CONTROL_CLR_REG);
++//            __raw_writel(clear_ctl, BALLOON3_NAND_CONTROL_CLR_REG);
++            writeb(clear_ctl,FLASHCTL_CLR);
 +        if (set_ctl)
-+            __raw_writel(set_ctl, BALLOON3_NAND_CONTROL_SET_REG);
++//            __raw_writel(set_ctl, BALLOON3_NAND_CONTROL_SET_REG);
++            writeb(set_ctl,FLASHCTL_SET);
 +#else
 +        balloon3_ctl &= (FLCE0 | FLCE1 | FLCE2 | FLCE3 | FLWP);
 +        balloon3_ctl |= (ctrl & NAND_CLE) ? FLCLE:0;
@@ -171,19 +176,19 @@
 +balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
 +{
 +    /* deselect all chips */
-+//    balloon3_ctl |= (FLCE0 | FLCE1 | FLCE2 | FLCE3);
-+    __raw_writel((FLCE0 | FLCE1 | FLCE2 | FLCE3), BALLOON3_NAND_CONTROL_SET_REG);
++    writeb(FLCE0 | FLCE1 | FLCE2 | FLCE3, FLASHCTL_SET);
++//    __raw_writel((FLCE0 | FLCE1 | FLCE2 | FLCE3), BALLOON3_NAND_CONTROL_SET_REG);
 +    /* do chip select as required */
 +    switch (chip) {
 +    case -1: break;
-+    case 0: //balloon3_ctl &= ~FLCE0; break;
-+        __raw_writel(FLCE0, BALLOON3_NAND_CONTROL_CLR_REG); break;
-+    case 1: //balloon3_ctl &= ~FLCE1; break;
-+        __raw_writel(FLCE1, BALLOON3_NAND_CONTROL_CLR_REG); break;
-+    case 2: //balloon3_ctl &= ~FLCE2; break;
-+        __raw_writel(FLCE2, BALLOON3_NAND_CONTROL_CLR_REG); break;
-+    case 3: //balloon3_ctl &= ~FLCE3; break;
-+        __raw_writel(FLCE3, BALLOON3_NAND_CONTROL_CLR_REG); break;
++    case 0: writeb(FLCE0, FLASHCTL_CLR); break;
++//        __raw_writel(FLCE0, BALLOON3_NAND_CONTROL_CLR_REG); break;
++    case 1: writeb(FLCE1, FLASHCTL_CLR); break;
++//        __raw_writel(FLCE1, BALLOON3_NAND_CONTROL_CLR_REG); break;
++    case 2: writeb(FLCE2, FLASHCTL_CLR); break;
++//        __raw_writel(FLCE2, BALLOON3_NAND_CONTROL_CLR_REG); break;
++    case 3: writeb(FLCE3, FLASHCTL_CLR); break;
++//        __raw_writel(FLCE3, BALLOON3_NAND_CONTROL_CLR_REG); break;
 +    }
 +//    writeb(balloon3_ctl,FLASHCTL);
 +}
@@ -207,6 +212,7 @@
 +
 +    balloon3_mtd->owner = THIS_MODULE;
 +
++printk("%s: doing ioremaps\n",__FUNCTION__);
 +#ifdef SPLIT_RANGE
 +    /* map physical io adress */
 +    balloon3_io_base = ioremap(balloon3_phys_io_base, SPLIT_RANGE_SIZE);
@@ -216,13 +222,21 @@
 +        return -EIO;
 +    }
 +    /* map physical ctl adress */
-+    balloon3_ctl_base = ioremap(balloon3_phys_ctl_base, SPLIT_RANGE_SIZE);
-+    if (!balloon3_ctl_base) {
++    balloon3_ctl_clr_base = ioremap(balloon3_phys_ctl_clr_base, SPLIT_RANGE_SIZE);
++    if (!balloon3_ctl_clr_base) {
 +        pr_err("ioremap to access Balloon3 NAND chip ctl failed\n");
 +        iounmap(balloon3_io_base);
 +        kfree(balloon3_mtd);
 +        return -EIO;
 +    }
++    balloon3_ctl_set_base = ioremap(balloon3_phys_ctl_set_base, SPLIT_RANGE_SIZE);
++    if (!balloon3_ctl_set_base) {
++        pr_err("ioremap to access Balloon3 NAND chip ctl failed\n");
++        iounmap(balloon3_ctl_clr_base);
++        iounmap(balloon3_io_base);
++        kfree(balloon3_mtd);
++        return -EIO;
++    }
 +#else
 +    balloon3_nand_base = ioremap(balloon3_phys_nand_base, NANDIO_LENGTH);
 +    if(!balloon3_nand_base){
@@ -232,6 +246,7 @@
 +    }
 +#endif
 +
++printk("%s: ioremaps done\n",__FUNCTION__);
 +    /* Get pointer to private data */
 +    this = (struct nand_chip *) (&balloon3_mtd[1]);
 +
@@ -241,10 +256,13 @@
 +
 +    /* Link the private data with the MTD structure */
 +    balloon3_mtd->priv = this;
++//printk("%s: writing to %lx\n",__FUNCTION__, BALLOON3_NAND_CONTROL_SET_REG);
 +
 +    /* initialise lines */
-+//    writeb(balloon3_ctl,FLASHCTL);
-+    __raw_writel((FLCE0 | FLCE1 | FLCE2 | FLCE3 | FLWP), BALLOON3_NAND_CONTROL_SET_REG);
++printk("%s: setting nand control lines inactive\n",__FUNCTION__);
++    writeb(FLCE0 | FLCE1 | FLCE2 | FLCE3 | FLWP, FLASHCTL_SET);
++//    __raw_writel((FLCE0 | FLCE1 | FLCE2 | FLCE3 | FLWP), BALLOON3_NAND_CONTROL_SET_REG);
++printk("%s: setting nand control lines inactive done\n",__FUNCTION__);
 +
 +    /* initialise mtd nand i/o */
 +    this->IO_ADDR_R = FLASHIO;
@@ -264,7 +282,8 @@
 +    {
 +#ifdef SPLIT_RANGE
 +        iounmap(balloon3_io_base);
-+        iounmap(balloon3_ctl_base);
++        iounmap(balloon3_ctl_clr_base);
++        iounmap(balloon3_ctl_set_base);
 +#else
 +        iounmap(balloon3_nand_base);
 +#endif
@@ -289,6 +308,7 @@
 +    add_mtd_partitions(balloon3_mtd, balloon3_partition_info, nr_partitions);
 +
 +    /* Return happy */
++printk("%s: complete\n",__FUNCTION__);
 +    return 0;
 +}
 +module_init(balloon3_nand_init);
@@ -303,7 +323,8 @@
 +
 +#ifdef SPLIT_RANGE
 +    iounmap(balloon3_io_base);
-+    iounmap(balloon3_ctl_base);
++    iounmap(balloon3_ctl_clr_base);
++    iounmap(balloon3_ctl_set_base);
 +#else
 +    iounmap(balloon3_nand_base);
 +#endif
@@ -318,9 +339,20 @@
 +MODULE_DESCRIPTION("Device specific logic for NAND flash on Balloon3 board");
 Index: include/asm-arm/arch-pxa/balloon3.h
 ===================================================================
---- include/asm-arm/arch-pxa/balloon3.h.orig    2010-06-12 06:15:57.000000000 +0100
-+++ include/asm-arm/arch-pxa/balloon3.h    2010-06-12 06:17:59.000000000 +0100
-@@ -52,6 +52,13 @@
+--- include/asm-arm/arch-pxa/balloon3.h.orig    2010-06-13 19:42:12.000000000 +0100
++++ include/asm-arm/arch-pxa/balloon3.h    2010-06-14 12:35:30.000000000 +0100
+@@ -33,8 +33,8 @@
+ #define BALLOON3_NANDIO_IO_REG         __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00000)
+ #define BALLOON3_INT_CONTROL_REG    __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e0000C) /* fpga/cpld interrupt control register */
+ #define BALLOON3_NANDIO_CTL2_REG     __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00010)
+-#define BALLOON3_NAND_CONTROL_CLR_REG     __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00014)
+-#define BALLOON3_NAND_CONTROL_SET_REG     __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e01014)
++#define BALLOON3_NANDIO_CTL_CLR_REG    __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00014)
++#define BALLOON3_NANDIO_CTL_SET_REG    __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e01014)
+ #define BALLOON3_VERSION_REG        __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e0001c)
+ 
+ #define BALLOON3_SAMOSA_ADDR_REG    __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00c00000)
+@@ -52,6 +52,14 @@
  /* backlight control */
  #define BALLOON3_GPIO_RUN_BACKLIGHT    (99)


@@ -329,7 +361,8 @@
 +#define BALLOON3_NANDIO_VIRT        BALLOON3_FPGA_VIRT
 +#define BALLOON3_NANDIO_IO_OFFSET      0x00e00000
 +#define BALLOON3_NANDIO_CTL2_OFFSET    0x00e00010
-+#define BALLOON3_NANDIO_CTL_OFFSET     0x00e00014
++#define BALLOON3_NANDIO_CTL_CLR_OFFSET     0x00e00014
++#define BALLOON3_NANDIO_CTL_SET_OFFSET     0x00e01014
 +


  #define BALLOON3_GPIO_S0_CD        (105)


Modified: balloon/branches/menuconfig/kernel/2.6.25.2/balloon3.patch
===================================================================
--- balloon/branches/menuconfig/kernel/2.6.25.2/balloon3.patch    2010-06-14 10:26:04 UTC (rev 1160)
+++ balloon/branches/menuconfig/kernel/2.6.25.2/balloon3.patch    2010-06-14 12:13:22 UTC (rev 1161)
@@ -1,7 +1,7 @@
 Index: include/asm-arm/arch-pxa/debug-macro.S
 ===================================================================
---- include/asm-arm/arch-pxa/debug-macro.S.orig    2010-06-12 06:12:38.000000000 +0100
-+++ include/asm-arm/arch-pxa/debug-macro.S    2010-06-12 06:13:02.000000000 +0100
+--- include/asm-arm/arch-pxa/debug-macro.S.orig    2008-05-07 00:21:32.000000000 +0100
++++ include/asm-arm/arch-pxa/debug-macro.S    2010-06-13 19:42:12.000000000 +0100
 @@ -18,7 +18,11 @@
          tst    \rx, #1            @ MMU enabled?
          moveq    \rx, #0x40000000        @ physical
@@ -17,7 +17,7 @@
 Index: include/asm-arm/arch-pxa/balloon3.h
 ===================================================================
 --- /dev/null    1970-01-01 00:00:00.000000000 +0000
-+++ include/asm-arm/arch-pxa/balloon3.h    2010-06-12 06:14:53.000000000 +0100
++++ include/asm-arm/arch-pxa/balloon3.h    2010-06-14 12:56:16.000000000 +0100
 @@ -0,0 +1,134 @@
 +/*
 + *  linux/include/asm-arm/arch-pxa/balloon3.h
@@ -155,8 +155,8 @@
 +#endif
 Index: include/asm-arm/arch-pxa/irqs.h
 ===================================================================
---- include/asm-arm/arch-pxa/irqs.h.orig    2010-06-12 06:12:38.000000000 +0100
-+++ include/asm-arm/arch-pxa/irqs.h    2010-06-12 06:13:02.000000000 +0100
+--- include/asm-arm/arch-pxa/irqs.h.orig    2008-05-07 00:21:32.000000000 +0100
++++ include/asm-arm/arch-pxa/irqs.h    2010-06-13 19:42:12.000000000 +0100
 @@ -181,7 +181,8 @@
  #elif defined(CONFIG_ARCH_LUBBOCK) || \
        defined(CONFIG_MACH_LOGICPD_PXA270) || \
@@ -189,8 +189,8 @@
  #define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
 Index: include/asm-arm/arch-pxa/uncompress.h
 ===================================================================
---- include/asm-arm/arch-pxa/uncompress.h.orig    2010-06-12 06:12:38.000000000 +0100
-+++ include/asm-arm/arch-pxa/uncompress.h    2010-06-12 06:13:02.000000000 +0100
+--- include/asm-arm/arch-pxa/uncompress.h.orig    2008-05-07 00:21:32.000000000 +0100
++++ include/asm-arm/arch-pxa/uncompress.h    2010-06-13 19:42:12.000000000 +0100
 @@ -14,7 +14,11 @@


  #define __REG(x)    ((volatile unsigned long *)x)
@@ -205,8 +205,8 @@
  static inline void putc(char c)
 Index: arch/arm/mach-pxa/Kconfig
 ===================================================================
---- arch/arm/mach-pxa/Kconfig.orig    2010-06-12 06:12:38.000000000 +0100
-+++ arch/arm/mach-pxa/Kconfig    2010-06-12 06:13:02.000000000 +0100
+--- arch/arm/mach-pxa/Kconfig.orig    2008-05-07 00:21:32.000000000 +0100
++++ arch/arm/mach-pxa/Kconfig    2010-06-14 12:56:07.000000000 +0100
 @@ -36,6 +36,11 @@
      bool "Intel HCDDBBVA0 Development Platform"
      select PXA27x
@@ -237,7 +237,7 @@
 Index: arch/arm/mach-pxa/balloon3.c
 ===================================================================
 --- /dev/null    1970-01-01 00:00:00.000000000 +0000
-+++ arch/arm/mach-pxa/balloon3.c    2010-06-12 06:13:02.000000000 +0100
++++ arch/arm/mach-pxa/balloon3.c    2010-06-14 12:56:07.000000000 +0100
 @@ -0,0 +1,361 @@
 +/*
 + *  linux/arch/arm/mach-pxa/balloon3.c
@@ -602,8 +602,8 @@
 +MACHINE_END
 Index: arch/arm/Kconfig
 ===================================================================
---- arch/arm/Kconfig.orig    2010-06-12 06:12:38.000000000 +0100
-+++ arch/arm/Kconfig    2010-06-12 06:13:02.000000000 +0100
+--- arch/arm/Kconfig.orig    2008-05-07 00:21:32.000000000 +0100
++++ arch/arm/Kconfig    2010-06-13 19:42:12.000000000 +0100
 @@ -790,7 +790,7 @@
             ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
             ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
@@ -615,8 +615,8 @@
        to provide useful information about your current system status.
 Index: arch/arm/mach-pxa/Makefile
 ===================================================================
---- arch/arm/mach-pxa/Makefile.orig    2010-06-12 06:12:38.000000000 +0100
-+++ arch/arm/mach-pxa/Makefile    2010-06-12 06:13:02.000000000 +0100
+--- arch/arm/mach-pxa/Makefile.orig    2008-05-07 00:21:32.000000000 +0100
++++ arch/arm/mach-pxa/Makefile    2010-06-14 12:56:18.000000000 +0100
 @@ -15,6 +15,7 @@
  obj-$(CONFIG_ARCH_LUBBOCK)    += lubbock.o
  obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
@@ -627,8 +627,8 @@
  obj-$(CONFIG_MACH_COLIBRI)    += colibri.o
 Index: Makefile
 ===================================================================
---- Makefile.orig    2010-06-12 06:12:38.000000000 +0100
-+++ Makefile    2010-06-12 06:13:02.000000000 +0100
+--- Makefile.orig    2008-05-07 00:21:32.000000000 +0100
++++ Makefile    2010-06-13 19:42:12.000000000 +0100
 @@ -190,8 +190,8 @@
  # Default value for CROSS_COMPILE is not to prefix executables
  # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile



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