Author: wookey
Date: 2010-03-19 18:31:02 +0000 (Fri, 19 Mar 2010)
New Revision: 1030
Modified:
balloon/trunk/bootldr/Makefile-level2
balloon/trunk/bootldr/boot-pxa.s
balloon/trunk/vhdl/fpga/balloon3.vhd
Log:
Merge novlio branch back into head, so that this becomes the default
build.
Use vlio patches in patches dir for vlio builds
Modified: balloon/trunk/bootldr/Makefile-level2
===================================================================
--- balloon/trunk/bootldr/Makefile-level2 2010-03-19 18:29:47 UTC (rev 1029)
+++ balloon/trunk/bootldr/Makefile-level2 2010-03-19 18:31:02 UTC (rev 1030)
@@ -18,8 +18,8 @@
#
VERSION_MAJOR = 3
-VERSION_MINOR = 1
-VERSION_MICRO = 2
+VERSION_MINOR = 2
+VERSION_MICRO = 0
VERSION_SPECIAL=
cvs_ver = BOOTLDR_${VERSION_MAJOR}_${VERSION_MINOR}_${VERSION_MICRO}
Modified: balloon/trunk/bootldr/boot-pxa.s
===================================================================
--- balloon/trunk/bootldr/boot-pxa.s 2010-03-19 18:29:47 UTC (rev 1029)
+++ balloon/trunk/bootldr/boot-pxa.s 2010-03-19 18:31:02 UTC (rev 1030)
@@ -2644,11 +2644,11 @@
// any slower cycles will be created by the VLIO timer in CPLD
// VLIO:
// RDF=3, RDN=7, RRR=6, RBUF=1, RBW=0, RT=4
-.long 0x74a47734
+//.long 0x74a47734
// No VLIO:
// SRAM timing for Samosa, asssuming 104MHz bus clock
// RDF=14, RDN=14, RRR=4, RBUF=0, RBW=0, RT=1
-//.long 0x74a44ee1
+.long 0x74a44ee1
//below is magic value for use with 'fast bus' mode - i.e if
//CPU_FREQ turned on in kernel
// RDF=13, RDN=13, RRR=5, RBUF=0, RBW=0, RT=1
Modified: balloon/trunk/vhdl/fpga/balloon3.vhd
===================================================================
--- balloon/trunk/vhdl/fpga/balloon3.vhd 2010-03-19 18:29:47 UTC (rev 1029)
+++ balloon/trunk/vhdl/fpga/balloon3.vhd 2010-03-19 18:31:02 UTC (rev 1030)
@@ -175,7 +175,7 @@
attribute init: string;
- constant Version_Minor : std_logic_vector(7 downto 0) := X"06";
+ constant Version_Minor : std_logic_vector(7 downto 0) := X"16";
constant CF_reset_state : std_logic_vector(7 downto 0)
:= -- '0' &
@@ -434,7 +434,7 @@
Port Map(
data_bus_in => cpu_data(15 downto 0),
data_bus_out => nand_data_out,
- cpu_nwe => cf_npwe,
+ cpu_nwe => cpu_nwe,
cpu_noe => cpu_noe,
cpu_rdnwr => cpu_rdnwr,
internal_RnS => internal_RnS,
@@ -508,7 +508,7 @@
-- data_bus_in => debug_data,
data_bus_out => samosa_data_out,
reg_add => cpu_a(4 downto 2),
- cpu_nwe => cf_npwe,
+ cpu_nwe => cpu_nwe,
cpu_noe => cpu_noe,
cpu_rdnwr => cpu_rdnwr,
samosa_select => samosa_select,
@@ -558,7 +558,7 @@
RESET_STATE => CF_reset_state,
D => cpu_data(7 downto 0),
register_select => cf_control_select,
- nWE => cf_npwe,
+ nWE => cpu_nwe,
EN => '1',
RnS => internal_RnS,
Q => cf_control,
@@ -571,7 +571,7 @@
RESET_STATE => cpu_Control_reset_state,
D => cpu_data(7 downto 0),
register_select => general_control_select,
- nWE => cf_npwe,
+ nWE => cpu_nwe,
EN => '1',
RnS => internal_RnS,
Q => control_latch,
@@ -584,7 +584,7 @@
RESET_STATE => X"00",
D => cpu_data(7 downto 0),
register_select => interupt_control_select,
- nWE => cf_npwe,
+ nWE => cpu_nwe,
EN => '1',
RnS => internal_RnS,
Q => interupt_control,
@@ -614,7 +614,8 @@
-- and when all IO is not parked. This is because the 48MHz clock
-- stops at standby/shutdown and VLIO operations can hang then.
vlio_disable <= '1' when samosa_park='1' and nand_park='1' else '0';
-cpu_rdy <= vlio_rdy when cpu_ncs4 = '0' and vlio_disable = '0' else '1';
+-- cpu_rdy <= vlio_rdy when cpu_ncs4 = '0' and vlio_disable = '0' else '1';
+cpu_rdy <= '1';
--vlio_nstart <= '0' when cpu_ncs4 = '0' and (cpu_noe = '0' or cf_npwe ='0') else '1';
vlio_nstart <= '0' when cpu_ncs4 = '0' else '1';
-- choose the delay
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