Author: wookey
Date: 2010-03-19 17:25:26 +0000 (Fri, 19 Mar 2010)
New Revision: 1026

Modified:
   balloon/trunk/bootldr/boot-pxa.s
Log:
Correction to MSC2_INIT comments to make patch clearer


Modified: balloon/trunk/bootldr/boot-pxa.s
===================================================================
--- balloon/trunk/bootldr/boot-pxa.s	2010-03-19 17:20:37 UTC (rev 1025)
+++ balloon/trunk/bootldr/boot-pxa.s	2010-03-19 17:25:26 UTC (rev 1026)
@@ -2642,12 +2642,11 @@
 // RDF is minimum number of clock cycles nOE/nPWE are asserted
 // we want this to be 3 for quick NAND access
 // any slower cycles will be created by the VLIO timer in CPLD
+// VLIO:
 // RDF=3, RDN=7, RRR=6, RBUF=1, RBW=0, RT=4
 .long 0x74a47734
-// 15  14 13 12 11 10 09 08 07 06 05 04 03  02 01 00
-//RBUF|  RRR   |    RDN    |    RDF    |RBW|   RT
-// for Samosa, asssuming 104MHz bus clock,
-// SRAM timing
+// No VLIO:
+// SRAM timing for Samosa, asssuming 104MHz bus clock
 // RDF=14, RDN=14, RRR=4, RBUF=0, RBW=0, RT=1
 //.long 0x74a44ee1
 //below is magic value for use with 'fast bus' mode - i.e if