library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bus_register is
	 generic ( Width : integer := 8 );
    Port ( reg_select : in std_logic;
			  data_in : in std_logic_vector((Width - 1) downto 0);
           data_out : out std_logic_vector((Width - 1) downto 0);
           nreset : in std_logic;
			  ResetState : std_logic_vector((Width - 1) downto 0);
           nwe : in std_logic);
end bus_register;

architecture Behavioral of bus_register is

   signal reg : std_logic_vector ((Width - 1) downto 0);
	
begin

	register_process: process ( nwe, reg_select, nreset )
	begin
		if ( nreset = '0' ) then
			reg <= ResetState;
		elsif ( nwe'event) and (nwe = '0') and (reg_select = '1') then
			reg <= data_in;
		end if;
	end process register_process;
	
	data_out <= reg;

end Behavioral;