library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity l3fpga is Port ( cpu_a : in std_logic_vector (25 downto 0); -- M1 cpu_d : inout std_logic_vector (31 downto 0); -- C2 cpu_rdy : out std_logic; -- B6 cpu_rdnwr : in std_logic; -- W3 cpu_noe : in std_logic; -- W4 cpu_nwe : in std_logic; -- AA4 cpu_ncs5 : in std_logic; -- Y1 cpu_ncs4 : in std_logic; -- Y2 cpu_ncs3 : in std_logic; -- Y3 cpu_ncs1 : in std_logic; -- AB4 cpu_ncs0 : in std_logic; -- F12 cpu_ncs2 : in std_logic; -- AA3 cpu_dqm0 : in std_logic; -- K2 cpu_dqm1 : in std_logic; -- L5 cpu_dqm2 : in std_logic; -- L6 cpu_dqm3 : in std_logic; -- L3 cpu_nsdcs3 : in std_logic; -- A12 cpu_nsdcs2 : in std_logic; -- B12 cpu_sdclk0 : in std_logic; -- Y11 nreset : in std_logic; -- D14 clk_48M : in std_logic; -- C12 bb_ib_dat0 : out std_logic; -- AA13 bb_ob_clk : in std_logic; -- Y13 bb_ob_stb : in std_logic; -- AB13 bb_ob_dat0 : in std_logic; -- U13 bb_ib_clk : out std_logic; -- W12 msl_clk_ext : inout std_logic; -- V13 bb_ib_stb : out std_logic; -- Y12 nand_d : inout std_logic_vector (15 downto 0); -- W13 nand_rnb : in std_logic; -- W16 nand_nwe : out std_logic; -- Y16 nand_nre : out std_logic; -- Y17 nand_nwp : out std_logic; -- AA17 nand_cle : out std_logic; -- U17 nand_ale : out std_logic; -- V17 nand_nce0 : out std_logic; -- W17 nand_nce1 : out std_logic; -- AA18 nand_nce2 : out std_logic; -- AB18 nand_nce3 : out std_logic; -- E14 nand_nce4 : out std_logic; -- E16 nand_nce5 : out std_logic; -- L1 bp_a : out std_logic_vector (25 downto 0); -- K22 bp_d : inout std_logic_vector (31 downto 0); -- W5 bp_noe : out std_logic; -- F20 bp_nwe : out std_logic; -- F21 bp_ncs2 : out std_logic; -- E22 bp_ncs3 : out std_logic; -- G17 bp_ncs4 : out std_logic; -- G18 bp_ncs5 : out std_logic; -- G19 bp_rd_nwr : out std_logic; -- F19 bp_sdclk1 : out std_logic; -- G21 bp_sdclk0 : out std_logic; -- G22 bp_dreq0 : in std_logic; -- K19 bp_dval0 : in std_logic; -- K20 bp_nreset : out std_logic; -- K21 bp_ext_rdy : in std_logic; -- C6 bp_nsktsel : out std_logic; -- W10 bp_cf_nrdy : in std_logic; -- Y10 bp_npce1 : out std_logic; -- AA10 bp_npce2 : out std_logic; -- AB10 bp_npoe : out std_logic; -- U10 bp_npwe : out std_logic; -- V10 bp_npior : out std_logic; -- AB11 bp_npiow : out std_logic; -- U11 bp_dqm0 : out std_logic; -- V22 bp_dqm1 : out std_logic; -- V20 bp_dqm2 : out std_logic; -- U19 bp_dqm3 : out std_logic; -- W20 bp_irq : in std_logic; -- F13 bp_npwait : in std_logic; -- A13 bp_niois16 : in std_logic; -- B13 bp_npreg : out std_logic; -- C13 bp_nstschg : in std_logic; -- D12 bp_cf_nreset : out std_logic; -- E12 cf_npoe : in std_logic; -- W21 cf_npwe : in std_logic; -- W19 cf_npce1 : in std_logic; -- V19 cf_npce2 : in std_logic; -- Y22 cf_niois16 : out std_logic; -- W22 cf_npwait : out std_logic; -- Y19 cf_npreg : in std_logic; -- Y21 cf_npior : inout std_logic; -- AB20 cf_npiow : in std_logic; -- L4 cf_npsktsel : in std_logic; -- Y4 aux_nirq : out std_logic; -- Y20 aux_unsuspend : out std_logic; -- D13 samosa_d : inout std_logic_vector (15 downto 0); -- F16 samosa_rnb : in std_logic; -- E17 samosa_absent : in std_logic; -- F17 samosa_reset : out std_logic; -- A15 samosa_irq : in std_logic; -- A18 samosa_nwe : out std_logic; -- B18 samosa_nre : out std_logic; -- C18 samosa_nwp : out std_logic; -- D18 samosa_cle : out std_logic; -- A19 samosa_ale : out std_logic; -- B19 samosa_nce : out std_logic; -- C19 samosa_wp : in std_logic; -- AA12 cif_dd : inout std_logic_vector (9 downto 0); -- A9 cif_pclk : inout std_logic; -- E11 cif_fv : inout std_logic; -- D11 cif_lv : inout std_logic; -- C11 cif_mclk : in std_logic; -- A11 pinko_txd : out std_logic; -- B15 pinko_rxd : in std_logic; -- D15 pinko_cts : out std_logic; -- E15 com1_bttxd : in std_logic; -- B20 com1_btrxd : out std_logic; -- E13 pxa_scl : in std_logic; -- A14 pxa_sda : inout std_logic; -- B14 lcd_pclk : in std_logic; -- AA11 lpclk_out : out std_logic; -- W9 green_led : out std_logic -- L2 ); end l3fpga; architecture Behavioral of l3fpga is --This is the generic Balloon 3 Component of which the CPLD interface is a subset of component Balloon3 generic ( Version : std_logic_vector(7 downto 0) := X"ff"; CPU_Address_Bus_Size : integer := 26; CPU_Data_Bus_Size : integer := 32; Backplane_Address_Bus_Size : integer := 26; Backplane_Data_Bus_Size : integer := 32 ); Port ( cpu_a : in std_logic_vector (CPU_Address_Bus_Size-1 downto 0); -- M1 cpu_data : in std_logic_vector (CPU_Data_Bus_Size-1 downto 0); -- C2 cpu_rdy : out std_logic; -- B6 cpu_rdnwr : in std_logic; -- W3 cpu_noe : in std_logic; -- W4 cpu_nwe : in std_logic; -- AA4 cpu_ncs5 : in std_logic; -- Y1 cpu_ncs4 : in std_logic; -- Y2 cpu_ncs3 : in std_logic; -- Y3 cpu_ncs1 : in std_logic; -- AB4 cpu_ncs0 : in std_logic; -- F12 cpu_ncs2 : in std_logic; -- AA3 cpu_dqm0 : in std_logic; -- K2 cpu_dqm1 : in std_logic; -- L5 cpu_dqm2 : in std_logic; -- L6 cpu_dqm3 : in std_logic; -- L3 cpu_nsdcs3 : in std_logic; -- A12 cpu_nsdcs2 : in std_logic; -- B12 cpu_sdclk0 : in std_logic; -- Y11 nreset : in std_logic; -- D14 clk_48M : in std_logic; -- C12 bb_ib_dat0 : out std_logic; -- AA13 bb_ob_clk : in std_logic; -- Y13 bb_ob_stb : in std_logic; -- AB13 bb_ob_dat0 : in std_logic; -- U13 bb_ib_clk : out std_logic; -- W12 msl_clk_ext : inout std_logic; -- V13 bb_ib_stb : out std_logic; -- Y12 nand_d : inout std_logic_vector (15 downto 0); -- W13 nand_rnb : in std_logic; -- W16 nand_nwe : out std_logic; -- Y16 nand_nre : out std_logic; -- Y17 nand_nwp : out std_logic; -- AA17 nand_cle : out std_logic; -- U17 nand_ale : out std_logic; -- V17 nand_nce0 : out std_logic; -- W17 nand_nce1 : out std_logic; -- AA18 nand_nce2 : out std_logic; -- AB18 nand_nce3 : out std_logic; -- E14 nand_nce4 : out std_logic; -- E16 nand_nce5 : out std_logic; -- L1 bp_a : out std_logic_vector (Backplane_Address_Bus_Size-1 downto 0); -- K22 bp_d : inout std_logic_vector (Backplane_Data_Bus_Size-1 downto 0); -- W5 bp_noe : out std_logic; -- F20 bp_nwe : out std_logic; -- F21 bp_ncs2 : out std_logic; -- E22 bp_ncs3 : out std_logic; -- G17 bp_ncs4 : out std_logic; -- G18 bp_ncs5 : out std_logic; -- G19 bp_rd_nwr : out std_logic; -- F19 bp_sdclk1 : out std_logic; -- G21 bp_sdclk0 : out std_logic; -- G22 bp_dreq0 : in std_logic; -- K19 bp_dval0 : in std_logic; -- K20 bp_nreset : out std_logic; -- K21 bp_ext_rdy : in std_logic; -- C6 bp_nsktsel : out std_logic; -- W10 bp_cf_nrdy : in std_logic; -- Y10 bp_npce1 : out std_logic; -- AA10 bp_npce2 : out std_logic; -- AB10 bp_npoe : out std_logic; -- U10 bp_npwe : out std_logic; -- V10 bp_npior : out std_logic; -- AB11 bp_npiow : out std_logic; -- U11 bp_dqm0 : out std_logic; -- V22 bp_dqm1 : out std_logic; -- V20 bp_dqm2 : out std_logic; -- U19 bp_dqm3 : out std_logic; -- W20 bp_irq : in std_logic; -- F13 bp_npwait : in std_logic; -- A13 bp_niois16 : in std_logic; -- B13 bp_npreg : out std_logic; -- C13 bp_nstschg : in std_logic; -- D12 bp_cf_nreset : out std_logic; -- E12 cf_npoe : in std_logic; -- W21 cf_npwe : in std_logic; -- W19 cf_npce1 : in std_logic; -- V19 cf_npce2 : in std_logic; -- Y22 cf_niois16 : out std_logic; -- W22 cf_npwait : out std_logic; -- Y19 cf_npreg : in std_logic; -- Y21 cf_npior : in std_logic; -- AB20 cf_npiow : in std_logic; -- L4 cf_npsktsel : in std_logic; -- Y4 aux_nirq : out std_logic; -- Y20 aux_unsuspend : out std_logic; -- D13 samosa_d : inout std_logic_vector (15 downto 0); -- F16 samosa_rnb : in std_logic; -- E17 samosa_absent : in std_logic; -- F17 samosa_reset : out std_logic; -- A15 samosa_irq : in std_logic; -- A18 samosa_nwe : out std_logic; -- B18 samosa_nre : out std_logic; -- C18 samosa_nwp : out std_logic; -- D18 samosa_cle : out std_logic; -- A19 samosa_ale : out std_logic; -- B19 samosa_nce : out std_logic; -- C19 samosa_wp : in std_logic; -- AA12 cif_dd : inout std_logic_vector (9 downto 0); -- A9 cif_pclk : inout std_logic; -- E11 cif_fv : inout std_logic; -- D11 cif_lv : inout std_logic; -- C11 cif_mclk : in std_logic; -- A11 pinko_txd : out std_logic; -- B15 pinko_rxd : in std_logic; -- D15 pinko_cts : out std_logic; -- E15 com1_bttxd : in std_logic; -- B20 com1_btrxd : out std_logic; -- E13 pxa_scl : in std_logic; -- A14 pxa_sda : inout std_logic; -- B14 lcd_pclk : in std_logic; -- AA11 lpclk_out : out std_logic; -- W9 green_led : out std_logic -- L2 ); end component; component Wishbone_Master is generic ( Version : std_logic_vector(15 downto 0) := X"0000"; Address_Bus_Size : integer := 26; Data_Bus_Size : integer := 32; IO_Bus_Size : integer := 8 ); Port ( data_in : in std_logic_vector (Data_Bus_Size-1 downto 0); data_out : out std_logic_vector (Data_Bus_Size-1 downto 0); address : in std_logic_vector (Address_Bus_Size-1 downto 0); nwe : in std_logic; noe : in std_logic; module_select : in std_logic; rdnwr : in std_logic; nreset : in std_logic; clock_in : in std_logic; io : inout std_logic_vector (IO_Bus_Size-1 downto 0) ); end component; constant version : std_logic_vector (7 downto 0):= X"4f"; signal cpu_d_dummy : std_logic_vector (31 downto 0); signal cpu_samosa_d : std_logic_vector(15 downto 0); constant WISHBONE_DATA_SIZE : integer := 32; constant WISHBONE_IO_SIZE : integer := 8; signal wish_clock : std_logic_vector(3 downto 0); signal wish_data_out : std_logic_vector(WISHBONE_DATA_SIZE-1 downto 0); begin Balloon3Part : Balloon3 generic map (Version => version, CPU_Address_Bus_Size => 26, CPU_Data_Bus_Size => 32, Backplane_Address_Bus_Size => 26, Backplane_Data_Bus_Size => 32 ) Port Map ( cpu_a => cpu_a, cpu_data => cpu_d, cpu_rdy => cpu_rdy, cpu_rdnwr => cpu_rdnwr, cpu_noe => cpu_noe, cpu_nwe => cpu_nwe, cpu_ncs5 => cpu_ncs5, cpu_ncs4 => cpu_ncs4, cpu_ncs3 => cpu_ncs3, cpu_ncs1 => cpu_ncs1, cpu_ncs0 => cpu_ncs0, cpu_ncs2 => cpu_ncs2, cpu_dqm0 => cpu_dqm0, cpu_dqm1 => cpu_dqm1, cpu_dqm2 => cpu_dqm2, cpu_dqm3 => cpu_dqm3, cpu_nsdcs3 =>cpu_nsdcs3, cpu_nsdcs2 =>cpu_nsdcs2, cpu_sdclk0 => cpu_sdclk0, nreset => nreset, clk_48M => clk_48M, bb_ib_dat0 => bb_ib_dat0, bb_ob_clk => bb_ob_clk, bb_ob_stb => bb_ob_stb, bb_ob_dat0 => bb_ob_dat0, bb_ib_clk => bb_ib_clk, msl_clk_ext => msl_clk_ext, bb_ib_stb => bb_ib_stb, nand_d => nand_d, nand_rnb => nand_rnb, nand_nwe => nand_nwe, nand_nre => nand_nre, nand_nwp => nand_nwp, nand_cle => nand_cle, nand_ale => nand_ale, nand_nce0 => nand_nce0, nand_nce1 => nand_nce1, nand_nce2 => nand_nce2, nand_nce3 => nand_nce3, nand_nce4 => nand_nce4, nand_nce5 => nand_nce5, bp_a => bp_a, bp_d => bp_d, bp_noe => bp_noe, bp_nwe => bp_nwe, bp_ncs2 => bp_ncs2, bp_ncs3 => bp_ncs3, bp_ncs4 => bp_ncs4, bp_ncs5 => bp_ncs5, bp_rd_nwr => bp_rd_nwr, bp_sdclk1 => bp_sdclk1, bp_sdclk0 => bp_sdclk0, bp_dreq0 => bp_dreq0, bp_dval0 => bp_dval0, bp_nreset => bp_nreset, bp_ext_rdy => bp_ext_rdy, bp_nsktsel => bp_nsktsel, bp_cf_nrdy => bp_cf_nrdy, bp_npce1 => bp_npce1, bp_npce2 => bp_npce2, bp_npoe => bp_npoe, bp_npwe => bp_npwe, bp_npior => bp_npior, bp_npiow => bp_npiow, bp_dqm0 => bp_dqm0, bp_dqm1 => bp_dqm1, bp_dqm2 => bp_dqm2, bp_dqm3 => bp_dqm3, bp_irq => bp_irq, bp_npwait => bp_npwait, bp_niois16 => bp_niois16, bp_npreg => bp_npreg, bp_nstschg => bp_nstschg, bp_cf_nreset => bp_cf_nreset, cf_npoe => cf_npoe, cf_npwe => cf_npwe, cf_npce1 => cf_npce1, cf_npce2 => cf_npce2, cf_niois16 => cf_niois16, cf_npwait => cf_npwait, cf_npreg => cf_npreg, cf_npior => cf_npior, cf_npiow => cf_npiow, cf_npsktsel => cf_npsktsel, aux_nirq => aux_nirq, aux_unsuspend => aux_unsuspend, samosa_d => samosa_d, samosa_rnb => samosa_rnb, samosa_absent => samosa_absent, samosa_reset => samosa_reset, samosa_irq => samosa_irq, samosa_nwe => samosa_nwe, samosa_nre => samosa_nre, samosa_nwp => samosa_nwp, samosa_cle => samosa_cle, samosa_ale => samosa_ale, samosa_nce => samosa_nce, samosa_wp => samosa_wp, cif_dd => cif_dd, cif_pclk => cif_pclk, cif_fv => cif_fv, cif_lv => cif_lv, cif_mclk => cif_mclk, pinko_txd => pinko_txd, pinko_rxd => pinko_rxd, pinko_cts => pinko_cts, com1_bttxd => com1_bttxd, com1_btrxd => com1_btrxd, pxa_scl => pxa_scl, pxa_sda => pxa_sda, lcd_pclk => lcd_pclk, lpclk_out => lpclk_out, green_led => green_led ); -- --WISHBONE Interface -- --wish_clock(0) -> 24M --wish_clock(1) -> 12M --wish_clock(2) -> 6M --wish_clock(3) -> 3M wishbone_clock_process: process(clk_48M) begin if (clk_48M'event and clk_48M = '1') then wish_clock <= wish_clock + 1; end if; end process wishbone_clock_process; Wishbone_Master_Interface : Wishbone_Master generic Map ( Version => X"0000", Address_Bus_Size => 26, Data_Bus_Size => WISHBONE_DATA_SIZE, IO_Bus_Size =>WISHBONE_IO_SIZE ) Port Map( data_in => cpu_d, data_out => wish_data_out, address => cpu_a, nwe => cpu_nwe, noe => cpu_noe, module_select => not cpu_ncs4, rdnwr => cpu_rdnwr, nreset => nreset, clock_in => wish_clock(3), io => cpu_samosa_d(7 downto 0) -- CMJ changed this because samosa_d is now used for real samosa interface ); end Behavioral;