-- $HDR$--
--+++++++++--
--Source Archived--
--Version in Repository:--
-- $Log:  25084: balloon3.vhd 
--
--   Rev 1.18    2/13/2008 12:15:02 AM  David
-- Switches PCMCIA npwe to a dummy since we on't want the PCMCIA bus excluding
-- it from the back plane.
--
--
--   Rev 1.17    2/13/2008 12:06:52 AM  David
-- CJ's BTRX mod added
--
--+++++++++--
----------------------------------------------------------------------------------
-- Company:
-- Engineer: david@itechnic.co.uk
-- 
-- Create Date:    14:00:50 06/30/2006 
-- Design Name: 
-- Module Name:    GenericL3 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Generic Balloon 3 interface glue for both CPLD and FPGA variants
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
--          0v1 - initial release with P2
--				?? - CMJ further mods for E1 board: I2C pullups, LCD pixel clock
-- Additional Comments: 
-- The following functions are not implemented in this version:
-- -- RS232 forwarding to the pinko connector or diversion from the backplane
-- -- Backplane data handling other than that required for CF

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Balloon3 is
	generic ( Version : std_logic_vector(7 downto 0) := X"00"; --Top byte comes from wrapper
				 CPU_Address_Bus_Size : integer := 26;
				 CPU_Data_Bus_Size : integer := 32;
				 Backplane_Address_Bus_Size : integer := 26;
				 Backplane_Data_Bus_Size : integer := 32
				);
	Port (
	cpu_a	    : in std_logic_vector (CPU_Address_Bus_Size-1 downto 0);
	cpu_data  : inout std_logic_vector (CPU_Data_Bus_Size-1 downto 0);
	cpu_rdy	 : out std_logic;
	cpu_rdnwr : in std_logic;
	cpu_noe	 : in std_logic;
	cpu_nwe	 : in std_logic;
	cpu_ncs5	 : in std_logic;
	cpu_ncs4	 : in std_logic;
	cpu_ncs3	 : in std_logic;
	cpu_ncs1	 : in std_logic;
	cpu_ncs0	 : in std_logic;
	cpu_ncs2	 : in std_logic;
	cpu_dqm0	 : in std_logic;
	cpu_dqm1	 : in std_logic;
	cpu_dqm2	 : in std_logic;
	cpu_dqm3	 : in std_logic;
	cpu_nsdcs3 : in std_logic;
	cpu_nsdcs2 : in std_logic;
	cpu_sdclk0 : in std_logic;
	nreset	  : in std_logic;
	clk_48M	  : in std_logic;
	bb_ib_dat0	 : out std_logic;
	bb_ob_clk	 : in std_logic;
	bb_ob_stb	 : in std_logic;
	bb_ob_dat0	 : in std_logic;
	bb_ib_clk	 : out std_logic;
	msl_clk_ext	 : inout std_logic;
	bb_ib_stb	 : out std_logic;
	nand_d	 : inout std_logic_vector (15 downto 0);
	nand_rnb	 : in std_logic;
	nand_nwe	 : out std_logic;
	nand_nre	 : out std_logic;
	nand_nwp	 : out std_logic;
	nand_cle	 : out std_logic;
	nand_ale	 : out std_logic;
	nand_nce0	 : out std_logic;
	nand_nce1	 : out std_logic;
	nand_nce2	 : out std_logic;
	nand_nce3	 : out std_logic;
	nand_nce4	 : out std_logic;
	nand_nce5	 : out std_logic;
	bp_a	    : out std_logic_vector (Backplane_Address_Bus_Size-1 downto 0);
	bp_d	    : inout std_logic_vector (Backplane_Data_Bus_Size-1 downto 0);
	bp_noe	 : out std_logic;
	bp_nwe	 : out std_logic;
	bp_ncs2	 : out std_logic;
	bp_ncs3	 : out std_logic;
	bp_ncs4	 : out std_logic;
	bp_ncs5	 : out std_logic;
	bp_rd_nwr : out std_logic;
	bp_sdclk1 : out std_logic;
	bp_sdclk0 : out std_logic;
	bp_dreq0	 : in std_logic;
	bp_dval0	 : in std_logic;
	bp_nreset	 : out std_logic;
	bp_ext_rdy	 : in std_logic;
	bp_nsktsel	 : out std_logic;
	bp_cf_nrdy	 : in std_logic;
	bp_npce1	 : out std_logic;
	bp_npce2	 : out std_logic;
	bp_npoe	 : out std_logic;
	bp_npwe	 : out std_logic;
	bp_npior	 : out std_logic;
	bp_npiow	 : out std_logic;
	bp_dqm0	 : out std_logic;
	bp_dqm1	 : out std_logic;
	bp_dqm2	 : out std_logic;
	bp_dqm3	 : out std_logic;
	bp_irq	 : in std_logic;
	bp_npwait	 : in std_logic;
	bp_niois16	 : in std_logic;
	bp_npreg	    : out std_logic;
	bp_nstschg	 : in std_logic;
	bp_cf_nreset : out std_logic;
	cf_npoe	 : in std_logic;
	cf_npwe	 : in std_logic;
	cf_npce1	 : in std_logic;
	cf_npce2	 : in std_logic;
	cf_niois16	 : out std_logic;
	cf_npwait	 : out std_logic;
	cf_npreg	 : in std_logic;
	cf_npior	 : in std_logic;
	cf_npiow	 : in std_logic;
	cf_npsktsel	 : in std_logic;
	aux_nirq	    : out std_logic;
	aux_unsuspend	 : out std_logic;
	samosa_d	    : inout std_logic_vector (15 downto 0);
	samosa_rnb	 : in std_logic;
	samosa_absent	 : in std_logic;
	samosa_reset	 : out std_logic;
	samosa_irq	 : in std_logic;
	samosa_nwe	 : out std_logic;
	samosa_nre	 : out std_logic;
	samosa_nwp	 : out std_logic;
	samosa_cle	 : out std_logic;
	samosa_ale	 : out std_logic;
	samosa_nce	 : out std_logic;
	samosa_wp	 : in std_logic;
	cif_dd	 : inout std_logic_vector (9 downto 0);
	cif_pclk	 : inout std_logic;
	cif_fv	 : inout std_logic;
	cif_lv	 : inout std_logic;
	cif_mclk	 : in std_logic;
	pinko_txd	 : out std_logic;
	pinko_rxd	 : in std_logic;
	pinko_cts	 : out std_logic;
	com1_bttxd	 : in std_logic;
	com1_btrxd	 : out std_logic;
	pxa_scl	 : in std_logic;
	pxa_sda	 : inout std_logic;
	lcd_pclk	 : in std_logic;
	lpclk_out	 : out std_logic;
	green_led	 : out std_logic
 );
end Balloon3;

architecture Behavioral of Balloon3 is

	attribute init: string;
	
	constant Version_Minor : std_logic_vector(7 downto 0) := X"02";

	constant CF_reset_state : std_logic_vector(7 downto 0)
					:=	-- '0' &
						-- '0' &
						-- '0' &
						-- '0' &
						-- '0' &
						-- '0' &	 --(10) Card interrupt source ? should also assert AUX_IRQ BP_CF_NRDY
						-- '0' &	 --( 9) Reserved for nBVD2
						-- '0' &	 --( 8) nBVD1 signal from card (NSTSCHNG)
						'0' &	 --( 7) VS2
						'0' &	 --( 6) VS1
						'0' &	 --( 5) Reserved for PCMCIA card detection on Mainstone (Balloon uses GPIO105)
						'0' &	 --( 4) Reset signal for CF card
						'0' &	 --( 3) Reserved for PCMCIA power management
						'0' &	 --( 2) Reserved for PCMCIA power management
						'0' &	 --( 1) Reserved for PCMCIA power management
						'0' ;   --( 0) Reserved for PCMCIA power management

	constant cpu_Control_reset_state : std_logic_vector(7 downto 0)
					:=	'0' &	 --(7) VS2
						'0' &	 
						'0' &	 --(5) Park NAND control lines.
						'0' &	 --(4) Park IO ready for power off.
						'0' &	 
						'0' &	 --(2) PINKO CTS
						'0' &	 --(1) PCMCIA Address Disable
					   '0';	 --(0) PCMCIA/CF Card Disable

--NAND Control
	signal nand_select : std_logic;
	signal nand_device_select : std_logic;
	signal nand_control_select : std_logic;
	signal nand_control2_select : std_logic;
	signal nand_data_out : std_logic_vector(15 downto 0);
	
-- SAMOSA
	signal samosa_irq_out : std_logic;
	signal samosa_select : std_logic;
	signal samosa_read_select : std_logic;
 	signal samosa_data_out  : std_logic_vector (15 downto 0);

--General Control Latch
	signal control_latch : std_logic_vector (7 downto 0);
	signal general_control_select : std_logic;
	
--Version
	signal version_select:    std_logic;
	signal version_out : std_logic_vector (15 downto 0);
	-- Upper nibble = 0x4 says I'm an FPGA = 0x8 says I'm a CPLD.
	-- 0xf indicates not there or unprogrammed.
	-- Next nibble = 0xf for debug/experimental version
	-- Otherwise this is the major version number.
	-- Upper byte comes from wrapper lower byte from here.
	-- lower byte is release number.

-- Reset Latch

--Interupt Control Latch
	signal interupt_control : std_logic_vector (7 downto 0);
	signal interupt_control_select : std_logic;
	signal interupt_status : std_logic_vector (7 downto 0);
	signal pcmcia_nrdy_latch : std_logic;
	signal pcmcia_nstschng_latch : std_logic;
	
--MODULES
	signal mod_add : std_logic_vector(7 downto 0);
	signal internal_reg : std_logic;
	signal samosa_reg : std_logic;
	constant BALLOON_INTERNAL     : std_logic_vector ( 7 downto 0):= X"e0"; --a(23..16)
	constant SAMOSA_ADDRESS       : std_logic_vector ( 7 downto 0):= X"c0"; --a(23..16)

--REGISTERS
	constant NUM_DECODE_BITS : integer := 12;
	signal reg_add : std_logic_vector(NUM_DECODE_BITS-1 downto 0);
	
	--Constants that define the internal register addresses
	constant NAND_ADD             : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"000"; -- a(11..0)
	constant CF_CONTROL_ADD       : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"008";
	constant NAND_CONTROL2_ADD    : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"010";
	constant NAND_CONTROL_ADD     : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"014";
	constant INTERUPT_CONTROL_ADD : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"00C";
	constant VERSION_ADD          : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"01C";
	constant GENERAL_CONTROL_ADD  : std_logic_vector (NUM_DECODE_BITS-1 downto 0):= X"01C";
		
	signal internal_read_select   : std_logic;
	signal internal_register_select : std_logic;

--PCMCIA
	signal pcmcia_select : std_logic;
	signal cf_control : std_logic_vector (7 downto 0);
	signal cf_control_select : std_logic;
	signal pcmcia_status : std_logic_vector (7 downto 0);
	signal pcmcia_nrdy : std_logic;
	signal pcmcia_nstschg : std_logic;
	signal pcmcia_enable_out : std_logic;
	signal pcmcia_data_out : std_logic_vector (15 downto 0);
	signal pcmcia_wants_bus : std_logic;
	signal pcmcia_stschng_int : std_logic;
	signal pcmcia_rdy_int : std_logic;
	signal cf_card_data : std_logic_vector(15 downto 0);
	signal cf_card_address : std_logic_vector(10 downto 0);
	signal dummy : std_logic;
	
--BACKPLANE
	signal bp_enable  : std_logic;
	signal backplane_read : std_logic;
	
	signal debug_data : std_logic_vector (15 downto 0);

--PXA BUS
	signal internal_dout : std_logic_vector (15 downto 0);

component bus_register is
	 generic ( Width : integer := 8 );
    Port ( reg_select : in std_logic;
			  data_in : in std_logic_vector((Width - 1) downto 0);
           data_out : out std_logic_vector((Width - 1) downto 0);
           nreset : in std_logic;
			  ResetState : std_logic_vector((Width - 1) downto 0);
           nwe : in std_logic);
end component;

component Balloon_nand is
	port (
			data_bus_in  : in std_logic_vector (15 downto 0);
			data_bus_out : out std_logic_vector (15 downto 0);
			cpu_nwe : in std_logic;
			cpu_noe : in std_logic;
			nand_device_select : in std_logic;
			nand_control_select : in std_logic;
			nand_control2_select : in std_logic;
			park_nand : in std_logic;
			nreset : in std_logic;
			nand_nre : out std_logic;
			nand_nwe : out std_logic;
			nand_cle : out std_logic;
			nand_ale : out std_logic;
			nand_nce0 : out std_logic;
			nand_nce1 : out std_logic;
			nand_nce2 : out std_logic;
			nand_nce3 : out std_logic;
			nand_nce4 : out std_logic;
			nand_nce5 : out std_logic;
			nand_nwp  : out std_logic;
			nand_chip_data : inout std_logic_vector(15 downto 0)
			);
			
end component;

component Balloon_pcmcia is
	port (
			data_bus_in : in std_logic_vector(15 downto 0);
			data_bus_out : out std_logic_vector(15 downto 0);
			address_bus : in std_logic_vector(10 downto 0);
			bus_rdnwr : in std_logic;
			nreset : in std_logic;
			want_bus : out std_logic;
			card_data : inout std_logic_vector(15 downto 0);
			card_address : out std_logic_vector(10 downto 0);
			park_interface : in std_logic;
			enable_pcmcia : in std_logic;
			address_enable : in std_logic;
			cpu_npoe : in std_logic;
			cpu_npce1 : in std_logic;
			cpu_npce2 : in std_logic;
			cpu_npior : in std_logic;
			cpu_npiow : in std_logic;
			cpu_npreg : in std_logic;
			cpu_npwe : in std_logic;
			cpu_npsktsel : in std_logic;
			cpu_niois16 : out std_logic;
			cpu_npwait : out std_logic;
			nstschng_out : out std_logic;
			nrdy_out : out std_logic;
			data_enable_out : out std_logic; --indicates when PCMCIA is driving the databus
			card_reset_in : in std_logic; -- source of card reset
			card_npoe : out std_logic;
			card_npce1 : out std_logic; --lower byte lane enable
			card_npce2 : out std_logic; --upper byte lane enable
			card_npior : out std_logic;
			card_npiow : out std_logic;
			card_npreg : out std_logic; --effectively a11
			card_npwe : out std_logic;  --card write enable
			card_niois16 : in std_logic; --card is 16 bits
			card_npwait : in std_logic; --wait from card
			card_reset : out std_logic; --reset out to card
			card_nstschng : in std_logic;
			card_nrdy : in std_logic
	);
			
end component;

component Balloon_samosa is
	port (
			data_bus_in : in std_logic_vector (15 downto 0);
			data_bus_out : out std_logic_vector (15 downto 0);
			reg_add : in std_logic_vector (2 downto 0); --a23..a21 selects SAMOSA control Latches
			cpu_nwe : in std_logic;
			cpu_noe : in std_logic;
			samosa_select : in std_logic;
			park_IO : in std_logic;
			nreset : in std_logic;
			samosa_reset_in : in std_logic;
			irq_out : out std_logic;
			samosa_irq : in std_logic;
			samosa_absent: in std_logic;
			samosa_nre : out std_logic;
			samosa_nwe : out std_logic;
			samosa_cle : out std_logic;
			samosa_ale : out std_logic;
			samosa_nce : out std_logic;
			samosa_nwp : out std_logic;
			samosa_reset_out : out std_logic;
			samosa_skt_data : inout std_logic_vector(15 downto 0)
			);
end component;

begin

Nand_Interface : Balloon_nand
	Port Map(
			data_bus_in => cpu_data(15 downto 0),
			data_bus_out => nand_data_out,
			cpu_nwe => cpu_nwe,
			cpu_noe => cpu_noe,
			nand_device_select => nand_device_select,
			nand_control_select => nand_control_select,
			nand_control2_select => nand_control2_select,
			park_nand => control_latch(5),
			nreset => nreset,
			nand_nre => nand_nre,
			nand_nwe => nand_nwe,
			nand_cle => nand_cle,
			nand_ale => nand_ale,
			nand_nce0 => nand_nce0,
			nand_nce1 => nand_nce1,
			nand_nce2 => nand_nce2,
			nand_nce3 => nand_nce3,
			nand_nce4 => nand_nce4,
			nand_nce5 => nand_nce5,
			nand_nwp => nand_nwp,
			nand_chip_data => nand_d
			);

PCMCIA_Interface : Balloon_pcmcia
	Port Map(
			data_bus_in => cpu_data(15 downto 0),
			data_bus_out => pcmcia_data_out,
			address_bus => cpu_a(10 downto 0),
			bus_rdnwr => cpu_rdnwr,
			nreset => nreset,
			want_bus => pcmcia_wants_bus,
			card_data => bp_d(15 downto 0),
			card_address => bp_a(10 downto 0),
			park_interface => control_latch(4),
			enable_pcmcia => not control_latch(0),
			address_enable => not control_latch(1),
			cpu_npoe => cf_npoe,
			cpu_npce1 => cf_npce1,
			cpu_npce2 => cf_npce2,
			cpu_npior => cf_npior,
			cpu_npiow => cf_npiow,
			cpu_npreg => cf_npreg,
			cpu_npwe => cf_npwe, --npwe is also used for all IO
			cpu_npsktsel => cf_npsktsel,
			cpu_niois16 => cf_niois16,
			cpu_npwait => cf_npwait,
			nstschng_out => pcmcia_nstschg,
			nrdy_out => pcmcia_nrdy,
			data_enable_out => pcmcia_enable_out,
			card_reset_in => cf_control(4),
			card_npoe => bp_npoe,
			card_npce1 => bp_npce1,
			card_npce2 => bp_npce2,
			card_npior => bp_npior,
			card_npiow => bp_npiow,
			card_npreg => bp_npreg,
			card_npwe => dummy,
			card_niois16 => bp_niois16,
			card_npwait => bp_npwait,
			card_reset => bp_cf_nreset,
			card_nstschng => bp_nstschg,
			card_nrdy => bp_cf_nrdy
	);
	
--The samosa bus is treated as a module with a specific address range
--Multiple SAMOSA buses can be created by creating multiple samosa_select lines from teh upper module addresses.
samosa_Interface : Balloon_samosa
	Port Map (
			data_bus_in => cpu_data(15 downto 0),
--			data_bus_in => debug_data,
			data_bus_out => samosa_data_out,
			reg_add => cpu_a(4 downto 2),
			cpu_nwe => cpu_nwe,
			cpu_noe => cpu_noe,
			samosa_select => samosa_select,
			park_IO => control_latch(4),
			nreset => nreset,
			samosa_reset_in => '1',
			irq_out => samosa_irq_out,
			samosa_irq => samosa_irq,
			samosa_absent => samosa_absent,
			samosa_nre => samosa_nre,
			samosa_nwe => samosa_nwe,
			samosa_cle => samosa_cle,
			samosa_ale => samosa_ale,
			samosa_nce => samosa_nce,
			samosa_nwp => samosa_nwp,
			samosa_reset_out => samosa_reset,
			samosa_skt_data => samosa_d
			);

--edge triggered interupt acknowledge
--This is not currently used however it it kept as a template in case it is needed.
pcmcia_nrdy_process : process (pcmcia_nrdy, interupt_control_select, nreset, cpu_nwe)
	begin
		if (nreset = '0') or ((cpu_nwe = '0') and (interupt_control_select = '1') and (cpu_data(0) = '1')) then
			 pcmcia_nrdy_latch <= '0';
		elsif (pcmcia_nrdy'event and pcmcia_nrdy = '0')    then
			pcmcia_nrdy_latch <= '1';
		end if;
	end process pcmcia_nrdy_process;
	
pcmcia_nstschng_process : process (pcmcia_nstschg, interupt_control_select, nreset, cpu_nwe)
	begin
		if (nreset = '0') or ((cpu_nwe = '0') and (interupt_control_select = '1') and (cpu_data(1) = '1')) then
			 pcmcia_nstschng_latch <= '0';
		elsif (pcmcia_nstschg'event and pcmcia_nstschg = '0')    then
			pcmcia_nstschng_latch <= '1';
		end if;
	end process pcmcia_nstschng_process;

-- version register at 0x10e0001c
	version_out <= Version & Version_Minor when ( version_select = '1' ) else X"0000";
						
--CF Control Latch at 0x10e00008
--Originally intended to imitate Mainstone PCMCIA0 register at 0x080000E0
--now balloonized
CF_Control_Register : bus_register Generic Map (Width => 8)
											  Port Map (  cf_control_select, cpu_data(7 downto 0), cf_control, nreset, CF_reset_state, cpu_nwe);

--Control latch at 0x10e0001c

cpu_Control_Register : bus_register Port Map (  general_control_select, cpu_data(7 downto 0), control_latch, nreset, cpu_Control_reset_state, cpu_nwe);

--Interrupt Mask at 0x10e0000c (write)
--zero in a bit enables the interrupt one masks it
cpu_Interrupt_Register : bus_register Port Map (  interupt_control_select, cpu_data(7 downto 0), interupt_control, nreset, X"00", cpu_nwe);

--Interrupt STATUS Register Bits (read)
--interupt_status <= "000000" & pcmcia_nstschng_latch & pcmcia_nrdy_latch;
--Masked interrupt bits
pcmcia_stschng_int <= ((not pcmcia_nstschg) and (not interupt_control(1)));
pcmcia_rdy_int     <= ((not pcmcia_nrdy) and (not interupt_control(0)));
interupt_status <= "000000" & pcmcia_stschng_int & pcmcia_rdy_int;
--pcmcia_status <= "00000" & pcmcia_nrdy & '0' & pcmcia_nstschg & '1' & '0' & "000000";
pcmcia_status <= "000000" & pcmcia_nstschg & pcmcia_nrdy;

--------------------------------------------------------------------------------------
--CPU DATA BUS Registers
  --ncs0 is Boot Rom
  --nCS1-nCS3 are off-board
  --nCS4 is NAND, latches and USB Host
	--nCS5 is Backplane
	
   --Balloon internal registers @ 0x10e
	--NAND   Data Bus         @ 0x10e00000
	--CF Control/Status       @ 0x10e00008
	--Interrupt Status/Ack    @ 0x10e0000c
	--NAND Control 2          @ 0x10e00010
	--NAND Control            @ 0x10e00014
	--General Control/Version @ 0x10e0001c
	
	--SAMOSA Registers are set from the SAMOSA module
	--SAMOSA base address @ 0x10c
	--SAMOSA registers    @ 0x10c00000 - 0x10c0001c

-- Internal Write Register Selects
-- reg_add represents the address used to select internal registers
-- mod_add the address that select between internal modules.
-- This code is a single module selected by BALLOON_INTERNAL
-- Individual chip selects are decoded here for the sub components so that we don't have to pass
-- the full address bus to each component and address decoding is controlled centrally

	reg_add <= cpu_a(11 downto 0) when (cpu_ncs4 = '0') else X"000"; -- Stops needless address select switching if it isnt for us
	mod_add <= cpu_a(23 downto 16) when (cpu_ncs4 = '0') else X"00";

--Build module address ranges	
	internal_reg    <= '1' when (mod_add = BALLOON_INTERNAL) else '0';
	samosa_reg      <= '1' when (mod_add = SAMOSA_ADDRESS)   else '0';
	
	-- NAND Module
	nand_device_select       <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = NAND_ADD) ) else '0';
	nand_control2_select     <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = NAND_CONTROL2_ADD) ) else '0';
	nand_control_select      <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = NAND_CONTROL_ADD) ) else '0';
	
	--PCMCIA Module
	cf_control_select        <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = CF_CONTROL_ADD) ) else '0';
	
	--General Balloon Registers
	interupt_control_select  <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = INTERUPT_CONTROL_ADD) ) else '0';
	version_select           <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = VERSION_ADD) ) else '0';
	general_control_select   <= '1' when ((cpu_ncs4 = '0') and (internal_reg = '1') and (reg_add = GENERAL_CONTROL_ADD) ) else '0';

	--SAMOSA Module
	samosa_select            <= '1' when ((cpu_ncs4 = '0') and (samosa_reg = '1')) else '0';
	
	
	--Bunch together the selects within a component that has multiple registers
	--(doing this just makes it easier to cut a module)
	nand_select <= nand_device_select or nand_control_select or nand_control2_select;
	
	--Bunch together all the component selects and generate the global reg read select
	internal_register_select <= nand_select or cf_control_select or interupt_control_select or version_select;
	internal_read_select <= '1' when (internal_register_select = '1' and cpu_noe = '0') else '0';
	samosa_read_select <= '1'   when (samosa_select = '1' and cpu_noe = '0') else '0';
	backplane_read <= '1' when ((cpu_ncs5 = '0') and (cpu_noe = '0')) else '0';

--Internal Read Registers

with reg_add select
	internal_dout <=
						nand_data_out when NAND_ADD,
						X"00" & pcmcia_status when CF_CONTROL_ADD,
						X"00" & interupt_status when INTERUPT_CONTROL_ADD,
					   version_out when VERSION_ADD,
						X"0000" when others;

------------------------------------------------------------------------------
--CPU BUS Data Control
--FIXME These should scale to the bus size.
--Note the backplane is only 16 bits of data here.
cpu_data(15 downto 0) <= internal_dout   when internal_read_select = '1' else "ZZZZZZZZZZZZZZZZ";
cpu_data(15 downto 0) <= samosa_data_out when samosa_read_select = '1'   else "ZZZZZZZZZZZZZZZZ";
cpu_data(15 downto 0) <= pcmcia_data_out when pcmcia_wants_bus = '1'     else "ZZZZZZZZZZZZZZZZ";
--cpu_data(CPU_Data_Bus_Size-1 downto 0) <= bp_d(CPU_Data_Bus_Size-1 downto 0) when backplane_read = '1' else "ZZZZZZZZZZZZZZZZ";
cpu_data(15 downto 0) <= bp_d(15 downto 0) when backplane_read = '1' else "ZZZZZZZZZZZZZZZZ";
--debug_data(15 downto 0) <= internal_dout   when internal_read_select = '1' else "ZZZZZZZZZZZZZZZZ";
--debug_data <= cpu_data(15 downto 0);

cpu_data(CPU_Data_Bus_Size-1 downto 16) <= (others => 'Z');

--BACKPLANE Data Control

--bp_enable <= '1' when (cf_npce1 = '0' or cf_npce2 = '0') else '0';
--bp_d(15 downto 0) <= cpu_d(15 downto 0) when (pcmcia_select = '1' and cf_npsktsel = '0' and cpu_rdnwr = '0') else "ZZZZZZZZZZZZZZZZ";

bp_nsktsel <= '1';

aux_unsuspend	<= '1';
--Direct Level Triggered Interrupts
--aux_nirq <= pcmcia_nrdy and pcmcia_nstschg;

--Masked interrupts
aux_nirq <= not( pcmcia_stschng_int or pcmcia_rdy_int);

--Acknowledged interrupts
--aux_nirq <= (not pcmcia_nrdy_latch) and (not pcmcia_nstschng_latch);

cpu_rdy <= '1';

pxa_sda <= 'Z';

pinko_txd	<=  '0';
pinko_cts	<=  '1';
-- allow external devices to talk to COM1
com1_btrxd	<=  'Z';

--DEBUG
--green_led <= nand_select;
--green_led <= not( pcmcia_stschng_int or pcmcia_rdy_int);
green_led <= not internal_register_select;

bb_ib_dat0 <= '0';
bb_ib_clk <= '0';
bb_ib_stb <= '1';
--bp_noe <= '1';
bp_noe <= '1' when (cpu_ncs5 = '1') else cpu_noe;
bp_npwe <= '1' when (cpu_ncs5 = '1') else cf_npwe;
lpclk_out <= lcd_pclk;
bp_dqm0 <= '0';
bp_dqm1 <= '0';
bp_dqm2 <= '0';
bp_dqm3 <= '0';
bp_sdclk0 <= '0';
bp_sdclk1 <= '0';
bp_ncs2 <= '1';
bp_ncs3 <= '1';
bp_ncs4 <= cpu_ncs4;
--bp_ncs5 <= '1';
bp_ncs5 <= cpu_ncs5;
bp_rd_nwr <= '0';
bp_nreset <= '1';

bp_a(Backplane_Address_Bus_Size-1 downto 0) <= cpu_a(Backplane_Address_Bus_Size-1 downto 0) when cpu_ncs5 = '0' else (others=>'Z');
--bp_a(Backplane_Address_Bus_Size-1 downto 0) <= cf_card_address when cpu_ncs5 = '1' else (others => 'Z');

bp_d(Backplane_Data_Bus_Size-1 downto 0) <= cpu_data(Backplane_Data_Bus_Size-1 downto 0) when (cpu_ncs5 = '0' and cf_npwe = '0') else (others=>'Z');

end Behavioral;