----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:09:03 07/11/2006 
-- Design Name: 
-- Module Name:    Wishbone_Master - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments:
-- Refer to the Wishbone Specification 
-- http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Wishbone_Master is
	generic ( Version : std_logic_vector(15 downto 0) := X"0000";
				 Address_Bus_Size : integer := 26;
				 Data_Bus_Size : integer := 32;
				 IO_Bus_Size : integer := 8
				);
	Port (
	data_in   : in  std_logic_vector (Data_Bus_Size-1 downto 0);
	data_out  : out std_logic_vector (Data_Bus_Size-1 downto 0);
	address   : in  std_logic_vector (Address_Bus_Size-1 downto 0);
	nwe : in std_logic;
	noe : in std_logic;
	module_select : in std_logic;
	rdnwr : in std_logic;
	nreset : in std_logic;
	clock_in : in std_logic;
	io : inout std_logic_vector (IO_Bus_Size-1 downto 0)
	);
	
end Wishbone_Master;

architecture Behavioral of Wishbone_Master is

--MODULES
	signal mod_add : std_logic_vector(7 downto 0);
	signal internal_reg : std_logic;

--REGISTERS
	constant NUM_DECODE_BITS : integer := 12; 
	signal reg_add : std_logic_vector(NUM_DECODE_BITS-1 downto 0);
	signal register_select : std_logic;

--Defines the address location of registers in the Wishbone Module
	constant WISHBONE_MODULE     : std_logic_vector ( 7 downto 0):= X"00"; --a(23..16)

--Wishbone Master Signals
--These need to be fulfilled from the interface port.
--NOTE: All wishbone signals are active high.
--      The RST_I signal is synchronous with CLK_I

	signal ADR_O : std_logic_vector(Address_Bus_Size-1 downto 0);
	signal DAT_I : std_logic_vector (Data_Bus_Size-1 downto 0);
	signal DAT_O : std_logic_vector (Data_Bus_Size-1 downto 0);
	signal WE_O  : std_logic;--indicates whether the current local bus cycle is a READ or WRITE cycle.
	signal STB_O : std_logic;--indicates a valid data transfer cycle.
	signal ACK_I : std_logic;--indicates the termination of a normal bus cycle.
	signal CYC_O : std_logic;--when asserted, indicates that a valid bus cycle is in progress.
	signal ERR_I : std_logic;--indicates an abnormal cycle termination.
	signal CLK_O : std_logic;
	signal RST_O : std_logic;

--Wishbone Slave
component simple_gpio
	Port (
	  clk_i : in std_logic;
	  rst_i : in std_logic;
	  cyc_i : in std_logic;
	  stb_i : in std_logic;
	  adr_i : in std_logic;
	  we_i : in std_logic;
	  dat_i : in std_logic_vector (7 downto 0);
	  dat_o : out std_logic_vector (7 downto 0);
	  ack_o : out  std_logic;
	  gpio : inout std_logic_vector (8 downto 1)
	  );
end component;

begin

--Register Address decoding
reg_add <= address(11 downto 0) when (module_select = '0') else X"000"; -- Stops needless address select switching if it isnt for us
mod_add <= address(23 downto 16) when (module_select = '0') else X"00";
	
internal_reg <= '1' when (mod_add = WISHBONE_MODULE) else '0';
register_select <= '1' when (internal_reg = '1' and reg_add = X"000") else '0';

--Interface to Wishbone Slave Module
WISBONE_IO : simple_gpio
Port Map (
  clk_i => CLK_O,
  rst_i => RST_O,
  cyc_i => CYC_O,
  stb_i => STB_O,
  adr_i => ADR_O(2),
  we_i => WE_O,
  dat_i => DAT_O(7 downto 0),
  dat_o => DAT_I(7 downto 0),
  ack_o => ACK_I,
  gpio => io(7 downto 0)
  );

CLK_O <= clock_in;

DAT_O <= data_in;
data_out <= DAT_I;
ADR_O <= address;

RST_O <= not nreset;
WE_O  <= not rdnwr when register_select = '1' else '0';
STB_O <= register_select;
CYC_O <= register_select;
end Behavioral;