--Balloon 3 CPLD Wrapper
-- david@itechnic.co.uk
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity l3cpld is
 Port (
   cpu_ncs2	 : in std_logic; 	-- 6
	cpu_d	 : inout std_logic_vector (15 downto 0);
	cpu_a	 : in std_logic_vector (23 downto 0); 	-- 33
	cpu_ncs0	 : in std_logic; 	-- 4
	cpu_ncs1	 : in std_logic; 	-- 3
	cpu_ncs3	 : in std_logic; 	-- 205
	cpu_ncs4	 : in std_logic; 	-- 197
	cpu_ncs5	 : in std_logic; 	-- 178
	cpu_rdy	 : inout std_logic; 	-- 206 OD 1
	cpu_nwe	 : in std_logic; 	-- 57
	cpu_noe	 : in std_logic; 	-- 56
	cpu_rdnwr	 : in std_logic; 	-- 55
	cpu_sdclk0	 : in std_logic; 	-- 182
	cpu_dqm1	 : in std_logic; 	-- 37
	cpu_dqm0	 : in std_logic; 	-- 38
	pxa_scl	 : in std_logic; 	-- 204
	pxa_sda	 : inout std_logic; 	-- 203
	pinko_txd	 : out std_logic; 	-- 202
	pinko_rxd	 : in std_logic; 	-- 201
	pinko_cts	 : out std_logic; 	-- 199
	green_led	 : out std_logic; 	-- 195
	com1_btrxd	 : out std_logic; 	-- 194
	com1_bttxd	 : in std_logic; 	-- 193
	nreset	 : in std_logic; 	-- 190
	bp_d	 : inout std_logic_vector (15 downto 0);
	bp_npior	 : out std_logic; 	-- 45
	bp_npiow	 : out std_logic; 	-- 46
	bp_npwe	 : out std_logic; 	-- 47
	bp_npoe	 : out std_logic; 	-- 48
	bp_npce1	 : out std_logic; 	-- 49
	bp_npreg	 : out std_logic; 	-- 60
	bp_niois16	 : in std_logic; 	-- 189
	bp_npce2	 : out std_logic; 	-- 188
	bp_cf_nrdy	 : in std_logic; 	-- 187
	bp_npwait	 : in std_logic; 	-- 30
	bp_nsktsel	 : out std_logic; 	-- 130
	bp_nstschg	 : in std_logic; 	-- 128
	bp_cf_nreset	 : out std_logic; 	-- 173
	bp_a	 : out std_logic_vector (10 downto 0); 	-- 120
	aux_nirq	 : inout std_logic; 	-- 59 OD 1
	samosa_reset	 : out std_logic; 	-- 198 1
	samosa_rnb	 : in std_logic; 	-- 159
	samosa_ale	 : out std_logic; 	-- 160
	samosa_cle	 : out std_logic; 	-- 161
	samosa_nwp	 : out std_logic; 	-- 162
	samosa_nre	 : out std_logic; 	-- 163
	samosa_nwe	 : out std_logic; 	-- 164
	samosa_absent	 : in std_logic; 	-- 166
	samosa_nce	 : out std_logic; 	-- 167
	samosa_d	 : inout std_logic_vector(15 downto 0);
	samosa_wp	 : in std_logic; 	-- 176
	samosa_irq	 : in std_logic; 	-- 172
	aux_unsuspend	 : out std_logic; 	-- 177
	nand_rnb	 : in std_logic; 	-- 175
	nand_nre	 : out std_logic; 	-- 168
	nand_nce5	 : out std_logic; 	-- 196
	nand_nce4	 : out std_logic; 	-- 192
	nand_nce3	 : out std_logic; 	-- 81
	nand_nce2	 : out std_logic; 	-- 169
	nand_nce1	 : out std_logic; 	-- 170
	nand_nce0	 : out std_logic; 	-- 171
	nand_nwp	 : out std_logic; 	-- 136
	nand_nwe	 : out std_logic; 	-- 135
	nand_ale	 : out std_logic; 	-- 133
	nand_cle	 : out std_logic; 	-- 132
	nand_d	 : inout std_logic_vector(15 downto 0);
	cf_npior	 : in std_logic; 	-- 78
	cf_npoe	 : in std_logic; 	-- 77
	cf_npce2	 : in std_logic; 	-- 76
	cf_npce1	 : in std_logic; 	-- 73
	cf_npsktsel	 : in std_logic; 	-- 58
	cf_npiow	 : in std_logic; 	-- 79
	cf_npwe	 : in std_logic; 	-- 80
	cf_npwait	 : out std_logic; 	-- 84
	cf_niois16	 : out std_logic; 	-- 129
	cf_npreg	 : in std_logic; 	-- 118
	lcd_pclk	 : in std_logic; 	-- 181
	clk_48m	 : in std_logic; 	-- 183
--	lpclk_out	 : out std_logic; 	-- 184 schematic error, lpclk out is connected to an input...
	spare	 : inout std_logic
 ); 
end l3cpld;

architecture Behavioral of l3cpld is
--This is the generic Balloon 3 Component of which the CPLD interface is a subset of
component Balloon3
	generic ( Version : std_logic_vector(7 downto 0) := X"00";
				 CPU_Address_Bus_Size : integer := 26;
				 CPU_Data_Bus_Size : integer := 32;
				 Backplane_Address_Bus_Size : integer := 26;
				 Backplane_Data_Bus_Size : integer := 32
	);
	Port (
	cpu_a	    : in std_logic_vector (CPU_Address_Bus_Size-1 downto 0);
	cpu_data  : inout std_logic_vector (CPU_Data_Bus_Size-1 downto 0);
	cpu_rdy	 : out std_logic;
	cpu_rdnwr : in std_logic;
	cpu_noe	 : in std_logic;
	cpu_nwe	 : in std_logic;
	cpu_ncs5	 : in std_logic;
	cpu_ncs4	 : in std_logic;
	cpu_ncs3	 : in std_logic;
	cpu_ncs1	 : in std_logic;
	cpu_ncs0	 : in std_logic;
	cpu_ncs2	 : in std_logic;
	cpu_dqm0	 : in std_logic;
	cpu_dqm1	 : in std_logic;
	cpu_dqm2	 : in std_logic;
	cpu_dqm3	 : in std_logic;
	cpu_nsdcs3 : in std_logic;
	cpu_nsdcs2 : in std_logic;
	cpu_sdclk0 : in std_logic;
	nreset	  : in std_logic;
	clk_48M	  : in std_logic;
	bb_ib_dat0	 : out std_logic;
	bb_ob_clk	 : in std_logic;
	bb_ob_stb	 : in std_logic;
	bb_ob_dat0	 : in std_logic;
	bb_ib_clk	 : out std_logic;
	msl_clk_ext	 : inout std_logic;
	bb_ib_stb	 : out std_logic;
	nand_d	 : inout std_logic_vector (15 downto 0);
	nand_rnb	 : in std_logic;
	nand_nwe	 : out std_logic;
	nand_nre	 : out std_logic;
	nand_nwp	 : out std_logic;
	nand_cle	 : out std_logic;
	nand_ale	 : out std_logic;
	nand_nce0	 : out std_logic;
	nand_nce1	 : out std_logic;
	nand_nce2	 : out std_logic;
	nand_nce3	 : out std_logic;
	nand_nce4	 : out std_logic;
	nand_nce5	 : out std_logic;
	bp_a	    : out std_logic_vector (Backplane_Address_Bus_Size-1 downto 0);
	bp_d	    : inout std_logic_vector (Backplane_Data_Bus_Size-1 downto 0);
	bp_noe	 : out std_logic;
	bp_nwe	 : out std_logic;
	bp_ncs2	 : out std_logic;
	bp_ncs3	 : out std_logic;
	bp_ncs4	 : out std_logic;
	bp_ncs5	 : out std_logic;
	bp_rd_nwr : out std_logic;
	bp_sdclk1 : out std_logic;
	bp_sdclk0 : out std_logic;
	bp_dreq0	 : in std_logic;
	bp_dval0	 : in std_logic;
	bp_nreset	 : out std_logic;
	bp_ext_rdy	 : in std_logic;
	bp_nsktsel	 : out std_logic;
	bp_cf_nrdy	 : in std_logic;
	bp_npce1	 : out std_logic;
	bp_npce2	 : out std_logic;
	bp_npoe	 : out std_logic;
	bp_npwe	 : out std_logic;
	bp_npior	 : out std_logic;
	bp_npiow	 : out std_logic;
	bp_dqm0	 : out std_logic;
	bp_dqm1	 : out std_logic;
	bp_dqm2	 : out std_logic;
	bp_dqm3	 : out std_logic;
	bp_irq	 : in std_logic;
	bp_npwait	 : in std_logic;
	bp_niois16	 : in std_logic;
	bp_npreg	    : out std_logic;
	bp_nstschg	 : in std_logic;
	bp_cf_nreset : out std_logic;
	cf_npoe	 : in std_logic;
	cf_npwe	 : in std_logic;
	cf_npce1	 : in std_logic;
	cf_npce2	 : in std_logic;
	cf_niois16	 : out std_logic;
	cf_npwait	 : out std_logic;
	cf_npreg	 : in std_logic;
	cf_npior	 : in std_logic;
	cf_npiow	 : in std_logic;
	cf_npsktsel	 : in std_logic;
	aux_nirq	    : out std_logic;
	aux_unsuspend	 : out std_logic;
	samosa_d	    : inout std_logic_vector (15 downto 0);
	samosa_rnb	 : in std_logic;
	samosa_absent	 : in std_logic;
	samosa_reset	 : out std_logic;
	samosa_irq	 : in std_logic;
	samosa_nwe	 : out std_logic;
	samosa_nre	 : out std_logic;
	samosa_nwp	 : out std_logic;
	samosa_cle	 : out std_logic;
	samosa_ale	 : out std_logic;
	samosa_nce	 : out std_logic;
	samosa_wp	 : in std_logic;
	cif_dd	 : inout std_logic_vector (9 downto 0);
	cif_pclk	 : inout std_logic;
	cif_fv	 : inout std_logic;
	cif_lv	 : inout std_logic;
	cif_mclk	 : in std_logic;
	pinko_txd	 : out std_logic;
	pinko_rxd	 : in std_logic;
	pinko_cts	 : out std_logic;
	com1_bttxd	 : in std_logic;
	com1_btrxd	 : out std_logic;
	pxa_scl	 : in std_logic;
	pxa_sda	 : inout std_logic;
	lcd_pclk	 : in std_logic;
	lpclk_out	 : out std_logic;
	green_led	 : out std_logic
 );
end component;

	constant version   : std_logic_vector (7 downto 0):= X"4f";

-- The following is needed because the CPLD has a subset of the full Address bus.	

	signal cpu_address	:std_logic_vector (25 downto 0);

--The Following Represent Signals that do not appear in the CPLD interface.
--Inputs may need to be set to a default value.

	signal cpu_dqm2 : std_logic;
	signal cpu_dqm3 : std_logic;
	signal cpu_nsdcs2 : std_logic;
	signal cpu_nsdcs3 : std_logic;
	signal bb_ib_dat0 : std_logic;
	signal bb_ob_clk : std_logic;
	signal bb_ob_stb : std_logic;
	signal bb_ob_dat0 : std_logic;
	signal bb_ib_clk : std_logic;
	signal msl_clk_ext : std_logic;
	signal bb_ib_stb : std_logic;
	signal bp_noe : std_logic;
	signal bp_nwe : std_logic;
	signal bp_ncs2 : std_logic;
	signal bp_ncs3 : std_logic;
	signal bp_ncs4 : std_logic;
	signal bp_ncs5 : std_logic;
	signal bp_rd_nwr : std_logic;
	signal bp_sdclk1 : std_logic;
	signal bp_sdclk0 : std_logic;
	signal bp_dreq0 : std_logic;
	signal bp_dval0 : std_logic;
	signal bp_nreset : std_logic;
	signal bp_ext_rdy : std_logic;
	signal bp_dqm0 : std_logic;
	signal bp_dqm1 : std_logic;
	signal bp_dqm2 : std_logic;
	signal bp_dqm3 : std_logic;
	signal bp_irq : std_logic;
	signal cif_dd : std_logic_vector (9 downto 0);
	signal cif_pclk : std_logic;
	signal cif_fv : std_logic;
	signal cif_lv : std_logic;
	signal cif_mclk : std_logic;
	signal lpclk_out : std_logic; --sigal mopped up after schematic error in 0v1
begin

Balloon3Part : Balloon3
generic map (Version => version,
				 CPU_Address_Bus_Size => 26,
				 CPU_Data_Bus_Size => 16,
				 Backplane_Address_Bus_Size => 11,
				 Backplane_Data_Bus_Size => 16
				 )
Port Map (
	cpu_a => cpu_address,
	cpu_data => cpu_d,
	cpu_rdy => cpu_rdy,
	cpu_rdnwr => cpu_rdnwr,
	cpu_noe => cpu_noe,
	cpu_nwe => cpu_nwe,
	cpu_ncs5 => cpu_ncs5,
	cpu_ncs4 => cpu_ncs4,
	cpu_ncs3 => cpu_ncs3,
	cpu_ncs1 => cpu_ncs1,
	cpu_ncs0 => cpu_ncs0,
	cpu_ncs2 => cpu_ncs2,
	cpu_dqm0 => cpu_dqm0,
	cpu_dqm1 => cpu_dqm1, 
	cpu_dqm2 => cpu_dqm2,
	cpu_dqm3 => cpu_dqm3,
	cpu_nsdcs3 =>cpu_nsdcs3, 
	cpu_nsdcs2 =>cpu_nsdcs2, 
	cpu_sdclk0 => cpu_sdclk0,
	nreset => nreset,
	clk_48M => clk_48M,
	bb_ib_dat0 => bb_ib_dat0,
	bb_ob_clk => bb_ob_clk,
	bb_ob_stb => bb_ob_stb,
	bb_ob_dat0 => bb_ob_dat0,
	bb_ib_clk => bb_ib_clk,
	msl_clk_ext => msl_clk_ext,
	bb_ib_stb => bb_ib_stb,
	nand_d => nand_d,
	nand_rnb => nand_rnb,
	nand_nwe => nand_nwe,
	nand_nre => nand_nre,
	nand_nwp => nand_nwp,
	nand_cle => nand_cle,
	nand_ale => nand_ale,
	nand_nce0 => nand_nce0,
	nand_nce1 => nand_nce1,
	nand_nce2 => nand_nce2,
	nand_nce3 => nand_nce3,
	nand_nce4 => nand_nce4,
	nand_nce5 => nand_nce5,
	bp_a => bp_a,
	bp_d => bp_d,
	bp_noe => bp_noe,
	bp_nwe => bp_nwe,
	bp_ncs2 => bp_ncs2,
	bp_ncs3 => bp_ncs3,
	bp_ncs4 => bp_ncs4,
	bp_ncs5 => bp_ncs5,
	bp_rd_nwr => bp_rd_nwr,
	bp_sdclk1 => bp_sdclk1,
	bp_sdclk0 => bp_sdclk0,
	bp_dreq0 => bp_dreq0,  
	bp_dval0 => bp_dval0,
	bp_nreset => bp_nreset, 
	bp_ext_rdy => bp_ext_rdy,
	bp_nsktsel => bp_nsktsel,
	bp_cf_nrdy => bp_cf_nrdy,
	bp_npce1 => bp_npce1,
	bp_npce2 => bp_npce2,
	bp_npoe => bp_npoe,
	bp_npwe => bp_npwe,
	bp_npior => bp_npior, 
	bp_npiow => bp_npiow,
	bp_dqm0 => bp_dqm0,
	bp_dqm1 => bp_dqm1,
	bp_dqm2 => bp_dqm2,
	bp_dqm3 => bp_dqm3,
	bp_irq => bp_irq,
	bp_npwait => bp_npwait,
	bp_niois16 => bp_niois16,
	bp_npreg => bp_npreg,
	bp_nstschg => bp_nstschg,
	bp_cf_nreset => bp_cf_nreset,
	cf_npoe => cf_npoe,
	cf_npwe => cf_npwe,
	cf_npce1 => cf_npce1,
	cf_npce2 => cf_npce2,
	cf_niois16 => cf_niois16,
	cf_npwait => cf_npwait,
	cf_npreg => cf_npreg,
	cf_npior => cf_npior,
	cf_npiow => cf_npiow,
	cf_npsktsel => cf_npsktsel,
	aux_nirq => aux_nirq,
	aux_unsuspend => aux_unsuspend,
	samosa_d => samosa_d,
	samosa_rnb => samosa_rnb,
	samosa_absent => samosa_absent,
	samosa_reset => samosa_reset,
	samosa_irq => samosa_irq,
	samosa_nwe => samosa_nwe,
	samosa_nre => samosa_nre,
	samosa_nwp => samosa_nwp,
	samosa_cle => samosa_cle,
	samosa_ale => samosa_ale,
	samosa_nce => samosa_nce,
	samosa_wp => samosa_wp,
	cif_dd => cif_dd,
	cif_pclk => cif_pclk,
	cif_fv => cif_fv,
	cif_lv => cif_lv,
	cif_mclk => cif_mclk,
	pinko_txd => pinko_txd,
	pinko_rxd => pinko_rxd, 
	pinko_cts => pinko_cts,
	com1_bttxd => com1_bttxd,
	com1_btrxd => com1_btrxd,
	pxa_scl => pxa_scl,
	pxa_sda => pxa_sda,
	lcd_pclk => lcd_pclk,
	lpclk_out => lpclk_out,
	green_led => green_led
	);

--Constructs a full address bus from the patchy coverage on the CPLD.
--The L3 module expects unused addresses to be at 0

cpu_address(25 downto 0) <= "00" & cpu_a(23 downto 21) & "00000000" & cpu_a(12) & "0" & cpu_a(10 downto 0);

end Behavioral;